— An Ultrathin Diffusion Barrier Solution for Advanced Chip Copper Interconnects

Introduction

As semiconductor manufacturing advances toward 7 nm, 3 nm, and more advanced nodes, back-end copper interconnects face severe scaling bottlenecks. Traditional Ta/TaN metal stacked liner/barrier layers have a total thickness of approximately 4 nm, occupying considerable space in ultra-scaled wiring structures and limiting copper filling volume. Moreover, when copper film thickness scales down to 10 nm, severe grain boundary diffusion causes sharp resistivity surge, deteriorating chip conductivity and operational stability.
Targeting these industrial challenges, this research adopts sapphire-based in-situ growth technology to fabricate transfer-free MoS₂/graphene van der Waals heterostructures with an ultra-thin total thickness of merely 1 nm. In this composite system, graphene acts as an efficient copper diffusion barrier, while MoS₂ optimizes copper wettability to ensure continuous and dense ultra-thin copper films. As the core supporting platform for the entire heterostructure system, sapphire guarantees ultra-clean, defect-free, and high-performance 2D barrier layers. Combined with cross-sectional TEM and resistivity test data, this blog comprehensively analyzes the technical value and advantages of sapphire substrates for advanced copper interconnect applications.

1. Sapphire Substrate: An Irreplaceable Platform for In-Situ MoS₂/Graphene Heterostructure Fabrication

1.1 Transfer-Free In-Situ Heterostructure Fabrication Process

The entire heterostructure fabrication is completed on sapphire substrates without any film transfer steps, completely avoiding interfacial contamination and structural damage. The process consists of three core steps:
First, graphene substrate preparation. High-quality monolayer graphene is grown on sapphire wafers using the optimized CVD process mentioned in Blog 1, obtaining robust graphene/sapphire composite substrates with strong interfacial adhesion. Second, precursor deposition. A 1.0 nm-thick MoO₃ film is thermally evaporated on graphene at a stable deposition rate of 0.1 nm/s to ensure film uniformity. Third, sulfurization annealing. The sample is placed in a tube furnace at 850 °C and 50 Torr. With 200 sccm Ar as carrier gas, sulfur powder sublimated at 160 °C reacts with MoO₃ to form monolayer MoS₂. Finally, a complete sapphire/monolayer graphene/monolayer MoS₂ vertical heterostructure is successfully constructed.

1.2 Exclusive Technical Advantages of Sapphire Substrates

Compared with copper foil and silicon substrates, sapphire exhibits three irreplaceable advantages for heterostructure fabrication:
First, chemical inertness eliminates side reactions. Copper substrates react violently with MoO₃ and sulfur precursors, destroying heterojunction structures; silicon substrates easily form native oxide layers that contaminate 2D interfaces. In contrast, sapphire is chemically stable and inert to all precursors, ensuring pure and intact heterostructure morphology. Second, transfer-free growth achieves defect-free interfaces. No PMMA residue, water/oxygen contamination, or mechanical damage exists between graphene and MoS₂ layers, enabling tight van der Waals bonding and perfect interfacial integrity. Third, rigid substrate provides mechanical support. Monolayer graphene and MoS₂ are mechanically fragile with thicknesses below 0.7 nm. The rigid single-crystal sapphire substrate provides stable mechanical support to maintain large-area film continuity and structural integrity.

2. Performance Characterization of MoS₂/Graphene/Sapphire Stacked Structures

[Figure 1: Cross-sectional HRTEM of Cu/MoS₂/graphene/sapphire and resistivity curves of ultra-thin copper films]

2.1 Interfacial Structure Analysis via Cross-Sectional HRTEM

Cross-sectional HRTEM characterization of the 20 nm Cu/monolayer MoS₂/monolayer graphene/sapphire structure clearly resolves four layered regions with flat and clean interfaces under a 4 nm scale bar: rigid sapphire substrate at the bottom, followed by monolayer graphene, monolayer MoS₂, and top polycrystalline copper film, without interlayer mixing or interfacial voids.
The dual 2D layers achieve complementary functions and synergistic effects. Pure graphene exhibits extremely poor copper wettability, resulting in discrete and aggregated copper films during direct deposition. However, graphene possesses a densely packed atomic structure that effectively blocks copper atom diffusion toward the substrate, serving as an excellent diffusion barrier. The top MoS₂ layer significantly modulates surface properties, greatly improving copper wettability and enabling continuous, dense, and void-free polycrystalline copper films via room-temperature deposition.
The structural advantage is extremely prominent: the total thickness of the MoS₂/graphene composite barrier is only ~1 nm, compared with the traditional 4 nm-thick Ta/TaN stacked barrier. This ultra-thin design releases 75% of the wiring channel space, perfectly satisfying the scaling requirements of advanced semiconductor processes and reserving sufficient volume for copper filling to maintain interconnect conductivity.

2.2 Resistivity Performance of Ultra-Thin Copper Films

The resistivity of copper films with thicknesses ranging from 10 nm to 30 nm was systematically tested, with the intrinsic resistivity of pure copper (1.68 μΩ·cm) as the reference. The key experimental data are as follows: 30 nm Cu (3.67 μΩ·cm), 20 nm Cu (4.07 μΩ·cm), 15 nm Cu (5.23 μΩ·cm), and 10 nm Cu (7.70 μΩ·cm).
Core conclusions from the data: First, excellent resistivity stability. When the copper thickness scales from 30 nm down to 10 nm, the resistivity only doubles without catastrophic surge, fully meeting the conductivity requirements of ultra-scaled advanced interconnects. Second, outstanding process compatibility. The resistivity of 15 nm copper films matches that of copper grown on exfoliated high-quality monolayer MoS₂, proving that in-situ grown polycrystalline MoS₂ on sapphire does not degrade copper wettability or electrical performance. Third, superior performance over traditional schemes. The 2D heterostructure barrier simultaneously achieves ultra-thin thickness and low resistivity at the nanoscale, fundamentally solving the high-resistance failure problem of ultra-scaled copper interconnects.

3. Auxiliary Characterization Verifying High-Quality Heterostructure Films

Multiple supplementary characterizations confirm the high quality of sapphire-supported heterostructures. First, MoS₂ Raman spectra show a peak difference of 20.3 cm⁻¹, a signature characteristic of monolayer MoS₂, verifying successful synthesis of high-quality single-layer molybdenum disulfide. Second, cross-sectional TEM of graphene confirms continuous and defect-free atomic layers on sapphire, ensuring complete copper diffusion barrier performance. Third, comparative experiments verify the synergistic effect of the dual-layer structure: copper films deposited directly on bare graphene at room and high temperatures suffer from severe aggregation and discontinuity, while MoS₂-covered graphene substrates yield uniform and dense copper films, strongly demonstrating the optimization effect of the MoS₂/graphene heterostructure.

4. Two Core Application Tracks of Sapphire-Based 2D Material Systems

The sapphire-based in-situ growth technology establishes two fully implementable 2D material application systems, covering microelectronic devices and advanced chip interconnects:
High-performance 2D electronic devices. Bilayer graphene prepared via cyclic CVD on sapphire features high crystallinity and low defect density enabled by van der Waals epitaxy. It can serve as high-quality channel materials for field-effect transistors, achieving high carrier mobility and large drain current for high-frequency and low-power microelectronic applications.
Advanced semiconductor interconnects. Sapphire-grown MoS₂/graphene heterostructures completely replace conventional Ta/TaN metal barrier stacks. With an ultra-thin thickness of 1 nm, the composite layer realizes excellent copper diffusion suppression and superior copper wettability, resolving the contradiction between dimensional scaling and resistivity surge in advanced copper interconnects and supporting next-generation semiconductor process iteration.

5. Summary

With excellent chemical stability, structural rigidity, and interfacial adaptability, sapphire single-crystal substrates enable a fully in-situ, transfer-free, and zero-contamination 2D heterostructure fabrication system, eliminating inherent defects of traditional metal substrates. The functional-complementary MoS₂/graphene composite structure integrates graphene’s superior copper diffusion barrier capability and MoS₂’s excellent metal wettability. It achieves ultra-thin barrier thickness while maintaining low resistivity and high stability of ultra-scaled copper interconnect films. The sapphire-based 2D material integration technology features simple fabrication, scalable production, and outstanding performance, providing a novel and feasible technical solution for back-end copper interconnect scaling in advanced semiconductor chips with great scientific value and industrial transformation potential.